Capacitors having improved high frequency characteristics and large capacity have been in demand to perform an increased number of functions in semiconductor integrated circuits. To achieve high-speed capacitors, the frequency dependency thereof should be decreased by reducing the resistance of the electrodes therein. Moreover, to achieve large-capacity capacitors, the thickness of an insulating layer interposed between the capacitor electrodes should be reduced, the dielectric constant of the insulating layer should be large and/or the area of the capacitor electrodes should be increased.
Capacitors used in semiconductor devices may have the structure of a metal oxide semiconductor (MOS) type, PN junction type, polysilicon-insulator-polysilicon (PIP) type, metal-insulator-metal (MIM) type, etc. Unfortunately, the above capacitor structures (excepting the MIM type structure) may be limited in high frequency performance because it is typically difficult to reduce the resistance of semiconductor electrodes to levels comparable to other conductive materials such as metals.
Accordingly, in semiconductor devices requiring high-speed capacitors, thin film capacitors having the MIM type structure can be used to provide low-resistance capacitor electrodes. In particular, a thin film capacitor of the MIM type structure has been widely applied to precise analog semiconductor devices since its capacitance variation (due to a voltage or temperature change) is typically very small. To facilitate capacitor formation, multilayer-wiring processes have been developed to achieve high integration levels, and thus the manufacturing processes of the thin film capacitor having the MIM type structure typically use a multilayer-wiring process.
FIGS. 1a to 1i are views explaining a conventional method of fabricating a MIM-type thin film capacitor using a multilayer-wiring process. Referring to FIG. 1a, in the multilayer-wiring process, a first insulating layer 10 is formed to insulate a lower structure (not shown) which has already been formed on an active region of a semiconductor substrate. Thereafter, an aluminum layer 12 is deposited on the first insulating layer 10 to form a first wiring layer. Referring to FIGS. 1b and 1c, a photoresist pattern 14 is formed on the aluminum layer 12, and then the aluminum layer 12 is selectively removed by a photographic and etching process to form a lower capacitor electrode 12a.
Thereafter, referring to FIG. 1d, a second insulating layer 16 is formed on upper surfaces of the lower capacitor electrode 12a to insulate the first wiring layer from a second wiring layer to be formed during subsequent steps. Referring now to FIGS. 1e and 1f, a photoresist pattern 18 is formed on the second insulating layer 16, and then the second insulating layer 16 is selectively removed by a photographic and etching process to form a contact hole 20. Thereafter, referring to FIGS. 1g and 1h, an oxide layer is formed (e.g., deposited) on the surface of the second insulating layer 16 and the lower capacitor electrode 12a, to form a dielectric layer 22, and an aluminum layer is deposited on the dielectric layer 22 to form the second wiring layer. Thereafter, the aluminum layer is selectively removed by a photographic and etching process as shown in FIG. 1i, so that an upper capacitor electrode 24 is formed.
In forming the lower capacitor electrode 12a, the surface of the dielectric layer 22 formed on the lower capacitor electrode 12a is apt to become uneven or in the worst case, portions of the dielectric layer 22 formed on the edge portions of the contact hole may be cut off as shown in FIG. 2 because of overetching during the etching process for forming the contact hole. If this unevenness is present in the dielectric layer 22, the lower and upper capacitor electrodes 12a and 24 may become short circuited together.
Japanese Laid-Open Patent Application No. 5-299582 discloses the use of an oxide layer having a thickness of about 1300.ANG. as the dielectric layer to solve the short-circuit problem between the upper and lower capacitor electrodes. However, according to this conventional method, only thin film capacitors having very small capacitance of about 0.28fF/.mu.m can be obtained due to the increase in the dielectric layer's thickness, and thus the size of the semiconductor device should be increased to obtain a desired capacitance. Meanwhile, in the event the lower capacitor electrode is formed with an aluminum-series layer as described above, the dielectric layer to be formed on the lower capacitor electrode typically cannot be processed under a temperature of more than about 450.degree. C. due to the relatively inferior thermal characteristics of aluminum. This limitation may cause the quality of the dielectric layer to be reduced.
As described above, the conventional method of fabricating a thin film capacitor has drawbacks in that it cannot be easily applied to semiconductor devices which require high-speed and large-capacity capacitors. Thus, notwithstanding the above described process, there continues to be a need for improved methods of forming capacitors with high capacitance.